This invention relates generally to semiconductor devices and more particularly to methods for sputter deposition of high-k dielectric materials for transistor gate fabrication in the manufacture of semiconductor devices.
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact or electrode is energized to create an electric field in a channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric or gate oxide, such as silicon dioxide (SiO2), is formed over the channel region, typically by thermal oxidation. A gate electrode or gate contact (e.g., metal or doped polysilicon) is then formed over the gate dielectric, and the gate dielectric and gate electrode materials are then patterned to form a gate structure overlying the channel region of the substrate.
The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
However, there are electrical and physical limitations on the extent to which thickness of gate dielectrics formed of SiO2 can be reduced. For example, very thin SiO2 gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO2 gate dielectric layers provide a poor diffusion barrier to dopants, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions.
Recent efforts directed to MOS device scaling have accordingly focused on alternative dielectric materials which can be formed in a thicker layer than scaled SiO2, and yet which produce equivalent field effect performance. These materials have dielectric constants greater than that of SiO2 and are commonly referred to as high-k materials or high-k dielectrics. The relative performance of these high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2. Because the dielectric constant is higher, a thicker high-k dielectric layer can be deposited to avoid or mitigate tunneling leakage currents, while still achieving the required value of EOT that is comparable to the EOT value of a thinner layer of thermally grown SiO2.
High-k dielectrics are typically deposited directly over a silicon substrate to form a gate dielectric layer using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes. One particular form of PVD deposition involves sputtering, wherein high-k dielectric films may be formed over silicon substrates in a sputtering chamber. Many high-k materials explored thus far include oxygen and/or nitrogen components, such as oxides, oxynitrides, or nitrides. In sputter deposition of such materials, the silicon substrate reacts with the oxygen and/or nitrogen, resulting in oxidation and/or nitridation at the interface between the substrate and the high-k gate dielectric. The performance and reliability of the resulting transistors, in turn, is dependent upon the quality of the interface between the high-k gate dielectric material and the underlying silicon, wherein oxidation or nitridation at the interface inhibits the ability to scale device dimensions and may degrade device performance.
For instance, excessive reaction of silicon during sputter deposition of oxides or oxynitrides causes formation of undesirable interface layers of SiO2-like material having a relatively low dielectric constant, resulting in increased EOT and thereby limiting scalability. In such a case, the upper surface of the silicon substrate oxidizes during the initial stages of the deposition process, causing formation of an unintended low quality oxide layer between the substrate and the subsequently deposited high-k material. In some cases, the unintended interface can be as much as 30 xc3x85 thick, wherein the unintended low-k interface layer increases the EOT of the resulting gate structure, and therefore inhibits scalability. Furthermore, this unintended interface generally has uncompleted bonds, that act as interface charging centers, causing interface states. The high density of such interface states in the low quality oxide results in carrier mobility degradation in operation of the transistor, where the higher the density of the interface states, the greater the resulting mobility degradation. Moreover, the unintended oxide (e.g., SiO or SiO2) typically has defects, which degrade properties. In the case of high-k nitride and oxynitride materials, surface nitridation of the silicon during sputter deposition limits or inhibits carrier mobility in the resulting transistor.
Thus, transistor performance and scalability are degraded for conventional sputter deposition of high-k oxides, oxynitrides, and nitrides. Such conventional sputtering techniques employ relatively low pressures (less than about 3-5 mTorr) with relatively high partial pressures of reactant gases, short distances between the sputtering target and the wafer surface, and unbiased wafers. Attempts to combat the unintended oxidation and/or nitridation at the Si/high-k interface include the formation of an intentional interface buffer layer, such as a high quality SiO2 over the silicon substrate, prior to depositing the high-k material. However, this approach requires additional processing steps and creation of the buffer layer presents other processing challenges. Moreover, the intentional SiO2 buffer layer has a relatively low dielectric constant, whereby the goal of reduced EOT becomes more difficult and scalability is limited.
Therefore, there is a need for improved gate fabrication techniques by which high quality interfaces can be achieved between the underlying silicon and deposited high-k dielectrics without the need for formation of an intentional interface buffer layer, and which avoid or mitigate excessive reaction with reactant gases in a PVD sputter deposition operation.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to methods for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition of oxides, oxynitrides, or nitrides, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions, such as positively charged oxygen ions, nitrogen ions, or any positively charged ions causing adverse reaction with the silicon or other semiconductor body surface, during the sputter deposition process.
In accordance with various aspects of the invention, reduction of the undesirable nitridation and/or oxidation is achieved through use of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and/or low sputtering powers or power densities, alone or in combination. High sputter deposition pressure is employed to reduce the mean free path of oxygen or nitrogen or other reactive ions, thereby reducing the likelihood of such ions hitting the wafer and reacting therewith during high-k deposition. Wafer biasing is employed to repel or retard the kinetic energy of positively charged oxygen or nitrogen ions away from the wafer, by which unwanted reaction between such ions and the substrate can be reduced.
Increasing the spacing of the wafer relative to the sputtering target, and hence to the process plasma, facilitates neutralization of oxygen or nitrogen ions before they strike the wafer surface. Low partial pressures of reactant oxygen and/or nitrogen gases is employed during sputtering to minimize or reduce the amount of ions available to cause undesirable oxidation and/or nitridation of the wafer surface. Low sputtering power settings are employed to reduce the density of oxygen and/or nitrogen material hitting the wafer surface.
In accordance with another aspect of the invention, the sputtering operation may be a two-step process in which one or more of the above techniques are employed to reduce ionic bombardment of the semiconductor material and hence to minimize unwanted reaction with the substrate in an initial deposition step to form a first high-k dielectric layer portion covering the semiconductor body. A second step is then employed to complete deposition of the desired high-k gate dielectric layer.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.